1. Field of the Invention
The present invention relates generally to circuitry for use in protecting against microprocessor failure, and specifically to circuitry for recognizing such failure, whether resulting from hardware or software faults, and which causes the hardware independently of the associated software, to check the microprocessor operation. The present invention is particularly advantageously applicable to telecommunications equipment which must operate in outdoor environments which subject the equipment to harsh electrical conditions. In addition to use in protecting against fault conditions in microprocessors, the present invention is generally advantageously applicable to any circuitry which includes sequentially operating components, which can malfunction due to extraneous power surges to which the circuitry may be subjected.
2. Description of the Prior Art
When a microprocessor device is used in a harsh environment which is susceptible to lightning, and other electrical power surges, the possibility of an error being induced and occurring during software operation in a microprocessoor based system is likely. Assuming that the majority of the damage of the lightning hit or power surge is dissipated elsewhere within the system, it still remains likely that a short malfunction or electrical problem may be caused in the microprocessor, thereby confusing its operation. It is essential that the microprocessor does not continue running normally once its operation has become confused. A prior art circuit is often used which ensures that the microprocessor does not continue in normal operation.
Such a prior art circuit is known as a "watchdog timer" which is normally a basic counter which must be reset by the microprocessor periodically to prevent the watchdog timer from reaching its maximum or minimum count. If the timer does reach its maximum or minimum count, it assumes that the microprocessor has become lost or is operating erroneously and forces a hardware reset, or an interrupt to occur.
An example of such a prior art circuit is a counter which is reset each time that a specific address is written to. This is not a very reliable solution, since the software associated with the microprocessor will periodically use the same invariant instruction set to reset the watchdog timer. Since there is no variation in the data byte or address written to the circuit, the microprocessor will continue resetting the timer even after it has become entirely confused. This circuit is the simplest configuration in the prior art, and also the least costly.
Another known alternative is to devise a complex pseudo-random pattern which must be calculated in software and in external hardware simultaneously. The pattern must match precisely in order to reset the watchdog timer. This approach may consume quite a bit of external hardware, plus consuming vast amounts of processing time for the calculation of each watchdog timer reset. This circuit is the most complex and the most costly configuration of the prior art.
Some examples of the above described prior art circuits are U.S. Pat. No. 4,594,685, Watchdog Timer; U.S. Pat. No. 4,538,273, Dual Input Watchdog Timer; U.S. Pat. No. 4,118,792, Malfunction Detection System For a Microprocessor Based Programmable Controller; and U.S. Pat. No. 4,529,842, Automatic Fault Recovery Arrangement. All of the aforementioned prior art patents rely primarily on the correct operation of software with little or no checking of such software by the external hardware.
In accordance with the present invention, a pseudo-random pattern of correct command sequences is forced to prevent the circuit from resetting itself. A byte-wide binary counter is used to produce a fixed sequence of patterns which must occur in order to properly reset the watchdog timer. The counter is incremented after each successful reset. The next reset must match the pattern which exists in the counter, or the timer will time out and the processor will be interrrupted. The circuit can be accomplished by using a minimum of external components.